JOIN VSDOpen2020 and be a part of open-source revolution !!

VSDOpen 2020 was bigger and better !!

VSDOpen 2020 had LIVE Tutorial Session for first 3 days

VSDOpen 2020 showcased open-source analog IP’s

VSDOpen 2020 was for 4-days

View VSDOpen2020 last day conference!!

We are excited to showcase some masterpieces of work done by Research Interns over last year, and also, we are really excited to introduce you to novel techniques of learning and designing analog/digital IP’s. This time, we are about to showcase you a list of projects which was achieved for the very first time in the field of open-source.

To Begin with: First time in the open-source world,

1. We have open-source analog IPs built from scratch using OSU-180nm PDK, Magic and eSim EDA tools, by undergrad and post-grad students. Unbelievable!!

2. We displayed to the RISC-V community around the globe how you can design a basic RISC-V core in just 5-days from scratch using TL-Verilog and Makerchip IDE. Unbelievable!!

3. We released a cloud-based VSD-Intelligent Assessment Technology platform which enables VLSI training for all time-zones at one go and is about 99% effective compared to any other training around the globe.

4. We will show you how you can develop your own SoC using real 130nm PDK from Skywater and OpenLANE EDA tool-chain from efabless