AMD/Xilinx Vivado Design Suite is a toolset designed by Xilinx for the synthesis and analysis of HDL (Verilog\System Verilog or VHDL). It does have its own simulator, router, and IPintegrator.

This course covers the fundamentals of the Vivado Design Suite IDE flow that includes
- Creating a simple project (an example design for learning purposes)
- Explanation of the Vivado Design Suite Interface and useful options in details
- Simulating it using the Vivado simulator (behavioral simulation)
- Doing RTLAnalysis (viewing the circuit in terms of digital components i.e., adders, multiplexers, registers, etc,.)
- Writing up the constraints (pins locations properties, clocks, etc.,)
- Synthesize the design (exploring netlist)
- Doing place and route (add implementation runs)
- Generating the bitstream (binary file)
- Programming the device using Vivado Hardware Manager

If you are a student and just started learning the Xilinx FPGA chipset this course is for you
- OR -
If you are an FPGAhobbyist who is willing to learn Vivado for fun projects then you are at the right place to begin with
- OR -

Even if you are a working professional who is switching from other toolsets to AMD/Xilinx toolsets then you should be watching this series to make yourself familiar with the tool environment.
Happy Development!