In this course, we will teach VHDL circuit design. The fundamental concepts about VHDL circuit design will be provided. In addition, practical examples using FPGA development boards will be provided. Combinational and clocked logic circuit design will be explained by examples. We will use either VIVADO or MODELSIM platform for the simulation and development of VHDL designs. Some of the written codes will be loaded into FPGA cards for demonstration purposes.

We use MODELSIM for simulation of the VHDLcodes. In VHDLcircuit design, good knowledge of signal and variable objects is necessary, and the engineer should know the differences between signal and variable objects very well. The most confusing part between the signal and variable objects is that variable objects are updated immediately whereas update of the signal objects is not immediate. Clock division operation and behavior of the signal and variable objects are explained in details using MODELSIM simulations. The behaviors of the combinational and sequential circuits are clarified using MODELSIM simulations.

We use VIVADOplatform for simulation and circuit synthesis of the VHDLcodes. In fact, it is better to use the MODELSIMplatform for simulations and VIVADOplatform for circuit synthesis and FPGAprogramming. We indicate that a VHDL code which can be simulated may not be synthesizable, and we explain this concept providing examples on VIVADOplatform. Through the course, we provide many videos explaining VHDLlanguage for circuit design and use of MODELSIM and VIVADO platforms for simulation and circuit synthesis.