VSD - Functional Verification Using Embedded-UVM - Part 1

Rating 3.9 out of 5 (13 ratings in Udemy)
What you'll learn
- SoC design flow, role of Functional Verification
- Logic Modeling, Introduction to Verilog
- Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
- Simulation Technology, Discrete Event Simulation
- Verification Trends and Challenges
- Concepts and Principles of Functional Verification
- Testbench Architecture and Components
- Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be …
Duration 3 Hours 58 Minutes
Paid
Self paced
Beginner Level
English (US)
166
Rating 3.9 out of 5 (13 ratings in Udemy)
Go to the Course
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Paid
Self paced
Beginner Level
English (US)
166
Rating 3.9 out of 5 (13 ratings in Udemy)
Go to the Course