Embedded System Design with Xilinx Zynq FPGA and VIVADO

Rating 3.7 out of 5 (175 ratings in Udemy)

What you'll learn

Implmenting VIVADO Design Methodology and Zynq Architecture for FPGA Design.
Designing and Implementing Embedded Project on Vitis/VIVADO 2020.1 Tool
Design Custom Embedded System with Xilinx Zynq 7000 FPGA with VIVADO in VHDL
Create Custom AXI-4 Slave Led Controller IP with VIVADO IPI in VHDL.
Software Design for Embedded Application with VIVADO and SDK
To Create a bootable system capable of booting from the SD card and QSPI …

Rating 3.7 out of 5 (175 ratings in Udemy)

What you'll learn

Implmenting VIVADO Design Methodology and Zynq Architecture for FPGA Design.
Designing and Implementing Embedded Project on Vitis/VIVADO 2020.1 Tool
Design Custom Embedded System with Xilinx Zynq 7000 FPGA with VIVADO in VHDL
Create Custom AXI-4 Slave Led Controller IP with VIVADO IPI in VHDL.
Software Design for Embedded Application with VIVADO and SDK
To Create a bootable system capable of booting from the SD card and QSPI flash
Debug designs with SDK and Utilize Timer Resources of Processing System.
Design with VIVADO HLS and Export C/C++ Design into IP/RTL from HLS
VIVADO SDK application development in C

Description

Note: Course is updated with HLS Design Lab & Debugging Sessions.

Embedded System Design with Xilinx VIVADO Design Suit and Zynq FPGA is targeted for Hardware (FPGA) Design and Embedded enthusiast who want to upgrade and enhance their hardware(FPGA) Design Skills with State of Art Design Tools and FPGA from Xilinx. This course cover from Introduction to VIVADO, Intellectual Property (IP), IP Design Methodology, designing basic embedded system with Vivado and SDK, Creating custom AXI-4 Lite Led Controller IP, Programming Processing System (PS) of Zynq (i.e Zedboard) with Embedded Application projects from SDK , Utilizing Timer API and Debugging Features on SDK for Zynq PS, and Creating Boot Image of the Application Project for SD and QSPI flash of Zynq (ZedBoard).

Finally we have included the session on "Embedded Design with VIVADO HLS" this session includes the HLS Design Methodology, Synthesizing HLS C/C++ Project, Generating RTL/HDL from C/C++ and Exporting C/C++ project in to IP-XACT/ Pcore/Sys Gen Format.

So from this course you will able to get design/implementation skills of simple embedded system (Memory Test Application) to complex application design (utilizing Timer, Debugging etc.) and Create Bootable Image file of the application project.For more details please watch the demo video and some Free video of course.

Duration 9 Hours 58 Minutes

Paid

Self paced

All Levels

English (US)

1173

Rating 3.7 out of 5 (175 ratings in Udemy)

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